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[[File:AY-3-8500_pinout.png|thumb|350px]]The AY-3-8500 was designed to be powered by six 1.5V cells (9V). Its specified operation is at 6-7V and a maximum of 12V instead of the 5V standard for logic. The nominal clock was 2.0 MHz, yielding a 500ns pixel width. One way to generate such a clock is to divide a 14.31818 MHz 4X colorburst clock by 7, producing 2.045 MHz. It featured independent video outputs for left player, right player, ball, and playground+counter, that were summed using resistors, allowing designers to use a different luminance for each one. It was housed in a standard 28-pin DIP.