Editing AY-3-8500
Jump to navigation
Jump to search
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
Latest revision | Your text | ||
Line 28: | Line 28: | ||
|} | |} | ||
[[File:AY-3-8500_pinout.png|thumb|350px]]The AY-3-8500 was designed to be powered by six 1.5V cells (9V). Its specified operation is at 6-7V and a maximum of 12V instead of the 5V standard for logic. The nominal clock was 2.0 MHz, yielding a 500ns pixel width. One way to generate such a clock is to divide a 14.31818 MHz 4X colorburst clock by 7, producing 2.045 MHz. It featured independent video outputs for left player, right player, ball, and playground+counter, that were summed using resistors, allowing designers to use a different luminance for each one. It was housed in a standard 28-pin DIP. | [[File:AY-3-8500_pinout.png|thumb|350px]]The AY-3-8500 was designed to be powered by six 1.5V cells (9V). Its specified operation is at 6-7V and a maximum of 12V instead of the 5V standard for logic. The nominal clock was 2.0 MHz, yielding a 500ns pixel width. One way to generate such a clock is to divide a 14.31818 MHz 4X colorburst clock by 7, producing 2.045 MHz. It featured independent video outputs for left player, right player, ball, and playground+counter, that were summed using resistors, allowing designers to use a different luminance for each one. It was housed in a standard 28-pin DIP. | ||
− |